Title :
A VLSI module for IEEE floating-point multiplication/division/square root
Author :
Lu, Paul Y. ; Dawallu, Kevin
Author_Institution :
LSI Logic Corp., Menlo Park, CA, USA
Abstract :
The major objective of this VLSI module design is to determine how to modify a fast floating-point multiplier so that it can perform division and square root in accordance with IEEE standards. This has been achieved by applying the Newton-Ralphson iteration only on the mantissa and adjusting the iterated result by a rounding algorithm. Using 1.0-μm CMOS standard cell technology, the total area of this module is approximately 7.0 mm×6.5 mm, which is just 25% larger than the floating-point multiplier. The module can compute multiplication, division, and square root in 3, 31, and 43 cycles, respectively. The cycle time, under nominal conditions, is expected to be 20 ns
Keywords :
CMOS integrated circuits; VLSI; cellular arrays; digital arithmetic; dividing circuits; iterative methods; modules; multiplying circuits; 1 micron; 20 ns; 7 to 6.5 mm; CMOS standard cell technology; IEEE standards; Newton-Ralphson iteration; VLSI module design; cycle time; fast floating-point multiplier; floating point division; floating point square root; iterated result; mantissa; multiplier modification; rounding algorithm; CMOS technology; Circuits; Computer architecture; Design engineering; Digital signal processing; Large scale integration; Logic design; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63389
