Title :
Characteristics of the Capacitorless Double Gate Quantum Well Single Transistor DRAM
Author :
Ertosun, M. Günhan ; Saraswat, Krishna C.
Author_Institution :
Electr. Eng. Dept., Stanford Univ., Stanford, CA, USA
Abstract :
We characterize and optimize double gate (DG) single-transistor (1T) DRAM via extensive simulations. We propose a new kind of DRAM: lT-quantum well DRAM: which has a "storage pocket" for holes within the body. This memory gives the opportunity to engineer spatial hole distribution within the body of the device, which is not possible with the conventional 1T DRAMs. Using this novel device we demonstrate approximately 2 order of magnitude increase in the drain current (Id) difference between the reads of two states of the memory. We study the retention characteristics of this novel DRAM, and also investigate the effect of quantum well depth on the retention characteristics.
Keywords :
DRAM chips; circuit optimisation; quantum well devices; double gate quantum well single transistor DRAM; quantum well depth effect; spatial hole distribution; Capacitors; Doping; High K dielectric materials; III-V semiconductor materials; Lithography; MOSFETs; Random access memory; Silicon; Threshold voltage; Voltage control;
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 2009. SISPAD '09. International Conference on
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4244-3974-8
Electronic_ISBN :
1946-1569
DOI :
10.1109/SISPAD.2009.5290256
