DocumentCode
1944984
Title
Cluster´s last RAM: will dual-port RAM speed up a hierarchical cache multiprocessor ?
Author
Landgraf, M.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Davis, CA, USA
fYear
1990
fDate
21-23 Mar 1990
Firstpage
879
Abstract
Summary form only given. A hierarchical cache multiprocessor system is analyzed for improvement as standard main memory is replaced with dual-port RAM. Qualitative analysis indicates under what conditions dual-port RAM would be desired. A subsequent quantitative analysis, based on typical bus traffic conditions, outlines the extent of improvement attainable. Finally, a number of system variables affecting the analysis are considered for their effect on the use of dual-port RAM
Keywords
buffer storage; multiprocessing systems; random-access storage; bus traffic; dual-port RAM; hierarchical cache multiprocessor system; Cache memory; Computer architecture; Computer science; Data analysis; Multiprocessing systems; Random access memory; Read-write memory; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computers and Communications, 1990. Conference Proceedings., Ninth Annual International Phoenix Conference on
Conference_Location
Scottsdale, AZ
Print_ISBN
0-8186-2030-7
Type
conf
DOI
10.1109/PCCC.1990.101722
Filename
101722
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