Lateral Ge/SiGe/Si Hetero-Channel p-Type MOSFETs

Author

Chen, Chia-Yu ; Liu, Yang ; Kim, Jongchol ; Dutton, Robert W.

Author_Institution

Center for Integrated Syst., Stanford Univ., Stanford, CA, USA

fYear

2009

fDate

9-11 Sept. 2009

Firstpage

1

Lastpage

2

Abstract

To further device scaling, a new hetero-channel MOS device is considered. A novel Ge/SiGe/Si lateral hetero-channel pFET that can significantly reduce band-to-band tunnelling (BTBT) leakage, retain high current drivability, and good electrostatics is introduced in this paper. Through detailed BTBT model in PDE simulators the on-current and off current in pFETs are analyzed. The simulation results show one-order of magnitude reduction (>20) in minimum off current and high drive current. Lateral hetero-channel p-FET provides a promising solution for future highly scaled CMOS technology.

Keywords

Ge-Si alloys; MOSFET; elemental semiconductors; germanium; leakage currents; partial differential equations; semiconductor device models; silicon; tunnelling; BTBT model; Ge-SiGe-Si; PDE simulators; band-to-band tunnelling leakage; current drivability; electrostatics; highly scaled CMOS technology; lateral hetero-channel p-type MOSFET; off-current simulator; on-current simulator; pFET device; CMOS technology; Electrostatics; FETs; Germanium silicon alloys; MOS devices; MOSFETs; Permittivity; Photonic band gap; Potential well; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 2009. SISPAD '09. International Conference on

Conference_Location

San Diego, CA

ISSN

1946-1569

Print_ISBN

978-1-4244-3974-8

Electronic_ISBN

1946-1569

Type

conf

DOI

10.1109/SISPAD.2009.5290260

Filename

5290260