Multiobjective search based algorithms for circuit partitioning problem for acceleration of logic simulation

Author

Harikumer, S. ; Kumar, Shashi

Author_Institution

Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., New Delhi, India

fYear

1997

fDate

4-7 Jan 1997

Firstpage

239

Lastpage

242

Abstract

Speeding up logic simulation is important to reduce design time of complex systems. Hardware emulation through reconfigurable systems (RS) built using FPGA´s offer an cheap and efficient method to achieve the required speed-up. Emulation through RS poses some unique problems because of the limited circuit and I/O resources. A preparatory step for emulation using RS is to partition the circuit into as few parts as possible satisfying the resource constraints. This paper presents multi-objective search based optimal and approximate algorithms for circuit partitioning for this purpose

Keywords

VLSI; circuit analysis computing; field programmable gate arrays; logic CAD; logic partitioning; search problems; FPGA; approximate algorithms; circuit partitioning problem; hardware emulation; logic simulation acceleration; multiobjective search based algorithms; optimal algorithms; reconfigurable systems; resource constraints; Acceleration; Circuit simulation; Circuit testing; Computational modeling; Emulation; Field programmable gate arrays; Hardware; Logic circuits; Logic design; Partitioning algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1997. Proceedings., Tenth International Conference on

Conference_Location

Hyderabad

ISSN

1063-9667

Print_ISBN

0-8186-7755-4

Type

conf

DOI

10.1109/ICVD.1997.568082

Filename

568082