Multiobjective search based algorithms for circuit partitioning problem for acceleration of logic simulation

Speeding up logic simulation is important to reduce design time of complex systems. Hardware emulation through reconfigurable systems (RS) built using FPGA´s offer an cheap and efficient method to achieve the required speed-up. Emulation through RS poses some unique problems because of the limited circuit and I/O resources. A preparatory step for emulation using RS is to partition the circuit into as few parts as possible satisfying the resource constraints. This paper presents multi-objective search based optimal and approximate algorithms for circuit partitioning for this purpose