Title :
Design and implementation of a Multiplierless Reconfigurable DFT/DCT processor
Author :
Ho, H. ; Szwarc, V. ; Kwasniewski, T.
Author_Institution :
Commun. Res. Centre, Ottawa, ON, Canada
fDate :
June 28 2009-July 1 2009
Abstract :
A Multiplierless Reconfigurable DFT/DCT Processor (MRP) design suitable for multicarrier applications is presented. The MRP implementation is based on a Reconfigurable Systolic Array (RSA) architecture that supports N-point DFT or DCT computations. All multiplication blocks in the MRP circuit have been implemented using the CSE-BitSlice technique to reduce hardware usage, and power consumption. Simulation results show that the MRP DFT circuit implementations can be used in most OFDM modulation realizations required by broadband communication systems and compression schemes of major digital video standards. The reconfigurability of the MRP makes it suitable for Shape Adaptive DCT (SA-DCT) computations required by object based video coding systems.
Keywords :
OFDM modulation; bit-slice computers; broadband networks; program processors; video coding; BitSlice technique; OFDM modulation; broadband communication systems; compression schemes; hardware usage; multicarrier applications; multiplierless reconfigurable processor; power consumption; reconfigurable systolic array; video coding systems; Circuit simulation; Computational modeling; Computer architecture; Discrete cosine transforms; Energy consumption; Hardware; Materials requirements planning; OFDM modulation; Process design; Systolic arrays;
Conference_Titel :
Circuits and Systems and TAISA Conference, 2009. NEWCAS-TAISA '09. Joint IEEE North-East Workshop on
Conference_Location :
Toulouse
Print_ISBN :
978-1-4244-4573-8
Electronic_ISBN :
978-1-4244-4574-5
DOI :
10.1109/NEWCAS.2009.5290428
