DocumentCode :
1945891
Title :
ITester: A FPGA based high performance traffic replay tool
Author :
Zhang, Fuxing ; Xie, Yingke ; Liu, Junjie ; Luo, Layong ; Ning, Qingsong ; Wu, Xiaolong
Author_Institution :
Inst. of Comput. Technol., Beijing, China
fYear :
2012
fDate :
29-31 Aug. 2012
Firstpage :
699
Lastpage :
702
Abstract :
Packet replay is an important way to reproduce real traffic for network test. Many works focus on the performance and accuracy of packet generation based on hardware, such as NP and FPGA, in order to replace inefficient software based packet replay tools. However, limited onboard storage space constrains the size of trace file. In this paper, we design a novel FPGA based packet replay tool called iTester which supports to replay large trace file without impairing the performance and accuracy. It combines high-performance feature of FPGA with vast storage space in host PC. In RAM disk mode, file of Giga Bytes, depending on the memory size in host PC, can be replayed at 10Gbps while the average error of packet gap is kept within 10ns. Additionally, compared to copy with packet, it has a 69% performance improvement in RAM disk mode by adjusting the block size for memory copy.
Keywords :
field programmable gate arrays; logic design; logic testing; random-access storage; FPGA based high performance traffic replay tool; FPGA design; ITester; RAM disk mode; bit rate 10 Gbit/s; host PC; limited onboard storage space; memory copy; network test; packet generation; packet replay; software based packet replay tools; time 10 ns; Accuracy; Computer architecture; Engines; Field programmable gate arrays; Hardware; Random access memory; Software;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on
Conference_Location :
Oslo
Print_ISBN :
978-1-4673-2257-7
Electronic_ISBN :
978-1-4673-2255-3
Type :
conf
DOI :
10.1109/FPL.2012.6339156
Filename :
6339156
Link To Document :
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