Title :
A clamped through silicon via (TSV) interconnection for stacked chip bonding using metal cap on pad and metal column forming in via
Author :
Shen, Li-Cheng ; Chien, Chien-Wei ; Jaung, Jin-Ye ; Hung, Yin-Po ; Lo, Wei-Chung ; Hsu, Chao-Kai ; Lee, Yuan-Chang ; Cheng, Hsien-Chie ; Lin, Chia-Te
Author_Institution :
Electron. & Opto-Electron. Res. Lab. (EOL), Ind. Technol. Res. Inst. (ITRI), Hsinchu
Abstract :
To prevent potential yield loss, achieve TSV with higher aspect ratio, improve the bonding reliability, and reduce the process cost, a clamped through silicon via (C-TSV) interconnection for stacked chip bonding is proposed and developed in this paper. The metal cap on pad design can not only be a bonding layer for other stacked die on it, but also performs as a protection stopper for blind vias drilled from the wafer backside.
Keywords :
integrated circuit design; integrated circuit interconnections; integrated circuit reliability; integrated circuit yield; wafer bonding; bonding reliability; clamped through silicon via interconnection; metal cap; pad design; stacked chip bonding; yield loss; Aerospace industry; Costs; Drilling; Filling; Integrated circuit interconnections; Protection; Silicon; Stacking; Through-silicon vias; Wafer bonding;
Conference_Titel :
Electronic Components and Technology Conference, 2008. ECTC 2008. 58th
Conference_Location :
Lake Buena Vista, FL
Print_ISBN :
978-1-4244-2230-2
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2008.4550026
