Title :
Through silicon vias technology for CMOS image sensors packaging
Author :
Henry, D. ; Jacquet, F. ; Neyret, M. ; Baillin, X. ; Enot, T. ; Lapras, V. ; Brunet-Manquat, C. ; Charbonnier, J. ; Aventurier, B. ; Sillon, N.
Author_Institution :
CEA-LETI, MINATEC, Grenoble
Abstract :
In this paper a low temperature ´via-last´ technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. The design rules of the vias will be briefly described and then, the steps of the technology will be presented : glass wafer carrier bonding onto the silicon substrate, silicon thinning and backside technology including specific steps like double side lithography, silicon deep etching, silicon side wall insulation, vias metallization and final bumping. Morphological and electrical characterizations of the vias-last technology will be showed and discussed. Finally, a picture obtained with the TSV CMOS Image Sensor (TSV CIS) will be presented.
Keywords :
CMOS image sensors; elemental semiconductors; etching; lithography; semiconductor device packaging; silicon; wafer level packaging; CMOS image sensors wafer level packaging; backside technology; double side lithography; final bumping; glass wafer carrier bonding; metallization; silicon deep etching; silicon side wall insulation; silicon substrate; silicon thinning; through silicon vias technology; vias-last technology; CMOS image sensors; CMOS technology; Glass; Lithography; Packaging; Silicon on insulator technology; Temperature sensors; Through-silicon vias; Wafer bonding; Wafer scale integration; Advanced packaging; CMOS image sensors (CIS); Through Silicon Vias (TSV); Wafer level technologies;
Conference_Titel :
Electronic Components and Technology Conference, 2008. ECTC 2008. 58th
Conference_Location :
Lake Buena Vista, FL
Print_ISBN :
978-1-4244-2230-2
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2008.4550028