A Silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnect

Author

Kumagai, Kouichi ; Yoneda, Yuko ; Izumino, Hitoshi ; Shimojo, Hiroko ; Sunohara, Masahiro ; Kurihara, Takashi ; Higashi, Mitsutoshi ; Mabuchi, Yoshihiro

Author_Institution

Syst. Fabrication Technol. Inc., Yokohama

fYear

2008

fDate

27-30 May 2008

Firstpage

571

Lastpage

576

Abstract

A novel silicon interposer (SilP) BGA package (PKG) - SilP PKG - has been developed and qualified through test chip. It features three key process technologies; Cu-filled through Si via (TSV), fine pitch multi-layer wiring with Cu- plating, and micro-bump interconnect. The cost-conscious fabrication process flow has been developed based on the build-up print boards´ Cu-plating technology and Si wafer batch process. The SilP PKG reliability as an LSI package has been confirmed.

Keywords

ball grid arrays; copper; electroplating; integrated circuit interconnections; silicon; wafer level packaging; Cu; LSI package; Si; fabrication process; microbump interconnect; multilayer plating interconnect; multilayer wiring; print board; silicon interposer BGA package; test chip; through Si via; wafer batch; Bonding; Fabrication; Large scale integration; Lead; Packaging; Resins; Silicon; Testing; Through-silicon vias; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 2008. ECTC 2008. 58th

Conference_Location

Lake Buena Vista, FL

ISSN

0569-5503

Print_ISBN

978-1-4244-2230-2

Electronic_ISBN

0569-5503

Type

conf

DOI

10.1109/ECTC.2008.4550030

Filename

4550030