Title :
A high performance and low energy intra prediction hardware for High Efficiency Video Coding
Author :
Kalali, Ercan ; Adibelli, Yusuf ; Hamzaoglu, Ilker
Author_Institution :
Fac. of Eng. & Natural Sci., Sabanci Univ., Istanbul, Turkey
Abstract :
Intra prediction algorithm in the recently developed High Efficiency Video Coding (HEVC) standard has very high computational complexity. Therefore, in this paper, we propose novel techniques for reducing amount of computations performed by HEVC intra prediction algorithm, and therefore reducing energy consumption of HEVC intra prediction hardware. The proposed techniques significantly reduce the amount of computations performed by 4×4 and 8×8 angular prediction modes with a small comparison overhead without any PSNR and bit rate loss. We also designed and implemented a high performance HEVC intra prediction hardware for 4×4 and 8×8 angular prediction modes including the proposed techniques using Verilog HDL, and mapped it to a Xilinx Virtex 6 FPGA. The proposed techniques significantly reduce the energy consumption of the proposed hardware on this FPGA.
Keywords :
computational complexity; field programmable gate arrays; video coding; HEVC standard; Verilog HDL; Xilinx Virtex 6 FPGA; angular prediction modes; computational complexity; energy consumption; high efficiency video coding; low energy intraprediction hardware algorithm; Energy consumption; Equations; Field programmable gate arrays; Hardware; Hardware design languages; Mathematical model; Prediction algorithms;
Conference_Titel :
Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on
Conference_Location :
Oslo
Print_ISBN :
978-1-4673-2257-7
Electronic_ISBN :
978-1-4673-2255-3
DOI :
10.1109/FPL.2012.6339161