• DocumentCode
    1946132
  • Title

    System#: High-level synthesis of physical simulations for FPGA-based real-time execution

  • Author

    Köllner, Christian ; Adler, Nico ; Müller-Glaser, Klaus D.

  • Author_Institution
    Embedded Syst. & Sensors Eng., FZI Res. Center for Inf. Technol., Karlsruhe, Germany
  • fYear
    2012
  • fDate
    29-31 Aug. 2012
  • Firstpage
    731
  • Lastpage
    734
  • Abstract
    FPGA-accelerated real-time simulations of physical phenomena gain importance in the area of Hardware-in-the-Loop tests for electrified powertrain components. Especially the challenging timing requirements demand dedicated hardware solutions. We propose System#, which is a highly modular, flexible and extensible open source environment for synthesizing physical computations to FPGAs. We demonstrate its capabilities by using an existing model of a squirrel-cage induction machine. We oppose several design variants, using fixed point and floating point arithmetic, and various settings for schedule length and pipelining depth of arithmetic operators. We conclude that the synthesized designs are on the par with a manually optimized implementation. Moreover, our approach scales well by allowing a time/area tradeoff over a wide range.
  • Keywords
    digital simulation; field programmable gate arrays; fixed point arithmetic; floating point arithmetic; high level synthesis; mechanical engineering computing; pipeline arithmetic; power transmission (mechanical); public domain software; real-time systems; squirrel cage motors; vehicle dynamics; FPGA-accelerated real-time simulations; FPGA-based real-time execution; HiL simulations; System#; arithmetic operators; design variants; electrified powertrain components; fixed point arithmetic; flexible open source environment; floating point arithmetic; hardware-in-the-Loop tests; high-level synthesis; manually optimized implementation; physical computations; physical simulations; pipelining depth; schedule length; squirrel-cage induction machine; timing requirements; Algorithm design and analysis; Computational modeling; Field programmable gate arrays; Hardware; IP networks; Mathematical model; Resource management;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on
  • Conference_Location
    Oslo
  • Print_ISBN
    978-1-4673-2257-7
  • Electronic_ISBN
    978-1-4673-2255-3
  • Type

    conf

  • DOI
    10.1109/FPL.2012.6339164
  • Filename
    6339164