DocumentCode
1946136
Title
Vectorized fault simulation on the Cray X-MP supercomputer
Author
Ozguner, F. ; Daoud, R.
Author_Institution
Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA
fYear
1988
fDate
7-10 Nov. 1988
Firstpage
198
Lastpage
201
Abstract
A highly vectorized parallel fault simulation (VPFS) algorithm developed to take advantage of the specific hardware architecture of the Cray X-MP is described. The data structure is optimized to suit the constraints imposed by the design of the main memory on the Cray supercomputer. The implementation of VPFS on a Cray X-MP/24 achieved a peak performance of about 2.5*10/sup 9/ gate evaluations per second on one processor, for a maximal speedup of approximately=30 over scalar processing.<>
Keywords
circuit analysis computing; digital simulation; fault location; parallel algorithms; Cray X-MP supercomputer; gate evaluations; hardware architecture; memory constraints; optimized data structure; peak performance; speedup; vectorized parallel fault simulation; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer networks; Computer simulation; Constraint optimization; Data structures; Hardware; Supercomputers;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-0869-2
Type
conf
DOI
10.1109/ICCAD.1988.122493
Filename
122493
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