On Captureless Delay Test Points

Author

Thibeault, C. ; Hariri, Y. ; Hobeika, C.

Author_Institution

Electr. Eng. Dept., Ecole de Technol. Super., Montreal, QC, Canada

fYear

2009

fDate

June 28 2009-July 1 2009

Firstpage

1

Lastpage

4

Abstract

In this paper we present a new technique called captureless delay testing points (CDTP). This technique allows the detection of delay faults left uncovered by launch-on-capture transitions, with top-off random launch-on-shift patterns that do not require fast switching scan enable signals. The CDTP random patterns are internally generated, requiring virtually no additional test time or memory tester. Area/performance overhead and technical obstacles to automation are minimal. Results show that CDTP provides appreciable coverage increase with minimum overhead.

Keywords

CMOS integrated circuits; delays; integrated circuit testing; CDTP random patterns; CMOS processes; captureless delay test points; delay fault detection; launch-on-capture transitions; top-off random launch-on-shift patterns; Automatic testing; Built-in self-test; Delay; Design automation; Fault detection; Lab-on-a-chip; Logic testing; Paper technology; Semiconductor device measurement; Signal generators; Delay testing; launch-on-capture; launch-on-shift; scan-based testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems and TAISA Conference, 2009. NEWCAS-TAISA '09. Joint IEEE North-East Workshop on

Conference_Location

Toulouse

Print_ISBN

978-1-4244-4573-8

Electronic_ISBN

978-1-4244-4574-5

Type

conf

DOI

10.1109/NEWCAS.2009.5290447

Filename

5290447