Title :
Controllable parameters identification for high speed channel through signal-power integrity combined analysis
Author :
Choi, Myoung Joon ; Pandit, Vishram S. ; Ryu, Woong Hwan
Author_Institution :
Intel Corp., Folsom, CA
Abstract :
The optimization of high speed channel demands more challenging tasks such as estimating the noise from the interaction between signal nets and power nets, assessing the on-chip power delivery network (PDN) effectiveness, and including the power delivery (PD) to signal coupling noise into the channel budget. However, even just identifying what to optimize in high-speed channel is difficult task, and obtaining meaningful parameters including interaction between signal integrity and power integrity is more challenging. The proposed analysis method employs accurate and more effective ways to find controllable parameters to optimize the channel response for the best performance in the high speed channel considering both signal integrity (SI) and power integrity (PI) interactions by utilizing response decomposition in the time domain with worst case pattern consideration.
Keywords :
circuit noise; parameter estimation; switching circuits; time-domain analysis; channel response; high speed channel; on-chip power delivery network; parameter identification controllability; power integrity interactions; power nets; signal coupling noise; signal integrity; signal nets; signal-power integrity combined analysis; time domain decomposition; worst case pattern consideration; Cost function; Frequency; Parameter estimation; Performance analysis; Power grids; Power system modeling; Signal analysis; Signal processing; System-on-a-chip; Time domain analysis;
Conference_Titel :
Electronic Components and Technology Conference, 2008. ECTC 2008. 58th
Conference_Location :
Lake Buena Vista, FL
Print_ISBN :
978-1-4244-2230-2
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2008.4550042