Title :
Design of a VLSI hardware PET decoder
Author :
Ascia, G. ; Catania, V. ; Ficili, G.
Author_Institution :
Ist. di Inf. e Telecommun., Catania Univ., Italy
Abstract :
In this paper we present the design of a hardware architecture for real-time PET (Priority Encoding Transmission) decoding of MPEG-1 messages. The main features of the decoder are: pipeline architecture and parallelism in the execution of some critical phases in the decoding process. The estimated clock frequency is 50 MHz with a required silicon area of about 35 mm2. The total latency introduced to decode an MPEG-1 GOP made up of 30 frames, each of 320×240 pixels, is about 40 ms
Keywords :
VLSI; decoding; multimedia communication; pipeline processing; real-time systems; video signal processing; 240 pixel; 320 pixel; 40 ms; 50 MHz; 76800 pixel; MPEG-1 messages; VLSI; clock frequency; critical phases; decoding process; hardware PET decoder; pipeline architecture; priority encoding transmission; real-time PET; total latency; Clocks; Decoding; Delay; Encoding; Frequency estimation; Hardware; Pipelines; Positron emission tomography; Silicon; Very large scale integration;
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-8186-7755-4
DOI :
10.1109/ICVD.1997.568085
