Fast and accurate Single Bit Error injection into SRAM Based FPGAs

The design process of safety-aware FPGA designs does not only require a robust architecture, but also an appropriate method of verifying correct system behaviour in presence of errors. One error type, Single Event Upsets (SEU), are rare events, so technologies of either external- or internal error injection are used to emulate this kind of error. While external injection typically has a slow emulation speed, internal injection is faster but also prone to so-called injection side effects. This work introduces a flow together with a mathematical framework, which allows the variable trade-off between emulation accuracy and emulation speed.