High performance ASIP implementation of PBDI — A new intra-field deinterlacing method

Author

Aubertin, Philippe ; Mohammadi, Hossein Mahvash ; Savaria, Yvon ; Langlois, J. M Pierre

Author_Institution

Groupe de Rech. en Microelectron. et Microsystemes, Ecole Polytech. de Montreal, Montreal, QC, Canada

fYear

2009

fDate

June 28 2009-July 1 2009

Firstpage

1

Lastpage

4

Abstract

We present techniques used to create a high performance application-specific instruction-set processor (ASIP) implementation of the Pattern-Based Directional Interpolation (PBDI) intra-field deinterlacing algorithm. The proposed techniques focus primarily on an efficient utilization of the available memory bandwidth. They include the use of Very Long Instruction Words (VLIW) and an appropriate choice of custom instructions and application-specific registers in order to form a processing pipeline. We report a speedup factor of 1351 in comparison with a software-only implementation of the algorithm running on a general-purpose 32-bit RISC processor.

Keywords

application specific integrated circuits; instruction sets; microprocessor chips; ASIP; application-specific instruction-set processor; application-specific register; general-purpose RISC processor; intrafield deinterlacing method; pattern-based directional interpolation; very long instruction word; Application specific integrated circuits; Application specific processors; Bandwidth; Digital systems; Image edge detection; Interpolation; Pipelines; Reduced instruction set computing; Registers; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems and TAISA Conference, 2009. NEWCAS-TAISA '09. Joint IEEE North-East Workshop on

Conference_Location

Toulouse

Print_ISBN

978-1-4244-4573-8

Electronic_ISBN

978-1-4244-4574-5

Type

conf

DOI

10.1109/NEWCAS.2009.5290458

Filename

5290458