Transistor sizing and VDD scaling for low power CMOS circuits

Depending on the normalized switching power model, this paper develops two power optimization techniques. The first deals with transistor sizing problem and presents a scheme to size transistors according to a specific design goal. The second technique relies on the joint transistor sizing and supply voltage scaling for reducing the switching power dissipation under specific delay requirements. This technique exhibits superiority over the first for the considered technology processes: UMC 0.13 mum and the Predictive high-k 45 nm.