• DocumentCode
    1946702
  • Title

    Hardware implementation of motion blur removal

  • Author

    Chandrapala, Thusitha N. ; Cabral, L.M.A.P. ; Ahangama, S. ; Ambagahawaththa, T.S. ; Samarawickrama, J.G.

  • Author_Institution
    Dept. of Electron. & Telecommun. Eng., Univ. of Moratuwa, Moratuwa, Sri Lanka
  • fYear
    2012
  • fDate
    29-31 Aug. 2012
  • Firstpage
    243
  • Lastpage
    248
  • Abstract
    Motion Blur due to the relative motion between the camera and object can seriously degrade image quality. We present an FPGA based motion blur detection and correction algorithm which is implemented on top of a configurable soft-processor based architecture. The system consists of two main modules. The blur detection module identifies the blur length and angle, and the restoration module uses regularized inverse filtering to remove the motion blur. The Processing algorithms are implemented as separate cores on the FPGA fabric where the soft processor core is only used for managing system configuration. The system can achieve a frame rate of 15fps for a 720p HD video stream.
  • Keywords
    cameras; field programmable gate arrays; filtering theory; image motion analysis; image restoration; image sensors; microprocessor chips; modules; FPGA; HD video stream; blur angle; blur length; camera; hardware implementation; image quality degradation; motion blur correction algorithm; motion blur detection algorithm; motion blur removal; regularized inverse filtering; restoration module; soft-processor based architecture; Clocks; Computer architecture; Field programmable gate arrays; Hardware; Image restoration; Software; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on
  • Conference_Location
    Oslo
  • Print_ISBN
    978-1-4673-2257-7
  • Electronic_ISBN
    978-1-4673-2255-3
  • Type

    conf

  • DOI
    10.1109/FPL.2012.6339188
  • Filename
    6339188