Direct digital synthesis-based all-digital phase-locked loop

Author

Vezant, Benoit ; Mansuy, Cédric ; Bui, Hung Tien ; Boyer, François-Raymond

Author_Institution

Dept. of Appl. Sci., Univ. du Quebec a Chicoutimi, Chicoutimi, QC, Canada

fYear

2009

fDate

June 28 2009-July 1 2009

Firstpage

1

Lastpage

4

Abstract

In this paper, we present an architecture for a PLL that is based on DDS and that can be implemented using all-digital components. The local oscillator is based on a DDS that is clocked by a local oscillator and that is synchronized to a crystal reference using a negative feedback which is similar to a PLL. Even though the DDS uses a ring oscillator, the proposed design can provide a precise output clock in presence of process and temperature variations. The resulting system has deterministic jitter that is equal to 1 period of the ring oscillator. The system was validated using MATLAB/Simulink and was implemented on a Cyclone II FPGA. Measured experimental results confirm that the system works as expected.

Keywords

circuit feedback; clocks; crystal oscillators; digital phase locked loops; direct digital synthesis; field programmable gate arrays; jitter; Cyclone II FPGA; DDS; MATLAB; Simulink; all-digital phase-locked loop; crystal oscillator; direct digital synthesis; jitter; local oscillator; negative feedback; oscillator; output clock; Clocks; Jitter; Local oscillators; MATLAB; Negative feedback; Negative feedback loops; Phase locked loops; Ring oscillators; Synchronization; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems and TAISA Conference, 2009. NEWCAS-TAISA '09. Joint IEEE North-East Workshop on

Conference_Location

Toulouse

Print_ISBN

978-1-4244-4573-8

Electronic_ISBN

978-1-4244-4574-5

Type

conf

DOI

10.1109/NEWCAS.2009.5290469

Filename

5290469