Energy-efficiency of VLSI caches: a comparative study

We investigate the use of organizational alternatives that lead to more energy-efficient caches for contemporary microprocessors. Dissipative transitions are likely to be highly correlated and skewed in caches, precluding the use of simplistic hit/miss ratio based power dissipation models for accurate power estimations. We use a detailed register-level simulator for a typical pipelined CPU and its multi-level caches, and simulate the execution of the SPECint92 benchmarks to glean accurate transition counts. A detailed dissipation model for CMOS caches is introduced for estimating the energy dissipation based on electrical parameters of a typical circuit implementation and the transition counts collected by simulation. A block buffering scheme is presented to allow cache energy requirements to be reduced without increasing access latencies. We report results for a system with an off-chip L2 cache. We conclude that block buffering, with sub-banking to be very effective in reducing energy dissipation in the caches, and in the off-chip I/O pad drivers