High-level aging estimation for FPGA-mapped designs

As the state-of-the-art FPGA devices use the latest advancements in CMOS technology, they also face the reliability challenges of nano-scale CMOS. Transistor aging, mainly due to Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI), is a major reliability issue. In this paper, we present a tool to predict the amount of aging-induced degradation for designs mapped to FPGA devices, to help the designers, in an early phase of the design flow, to choose the appropriate mapping and/or optimization efforts, in order to prolong the lifetime of their FPGA-mapped designs. The tool is based on system level abstractions for both BTI and HCI device level models, in addition to implicit device-level information existed in the power and timing reports provided from the FPGA´s vendor tools. A case study of using the tool to explore different designs and mapping options shows that aging of the FPGA device is dependent on the design loaded onto it. Furthermore, different mappings and optimizations of the same circuit can result in different aging rates.