Title :
Using active cache to solve the bottleneck of bus in the parallel Radar signal process system
Author :
Fei, Qin ; Zheng, Wang ; Teng, Long
Author_Institution :
Sch. of Inf., Beijing Inst. of Technol.
Abstract :
Solving bottleneck of bus is becoming a challenging task in the design of parallel radar signal processing area. This paper has introduced a novel technology called active cache to solve this problem. By actively inserting the cache code into programs, the system will cache the remote data to local before using it. This approach is applied to the UTDSP benchmark suites, giving a good experiment result on an embedded signal processing system of four TigerSHARC101 DSPs
Keywords :
cache storage; digital signal processing chips; field buses; radar signal processing; TigerSHARC101 DSP; active cache; bus bottleneck; cache code; embedded signal processing system; parallel radar signal process system; Digital signal processing; Embedded computing; Informatics; Parallel architectures; Parallel machines; Parallel processing; Radar signal processing; Real time systems; Signal design; Signal processing;
Conference_Titel :
Signal Processing, 2006 8th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-9736-3
Electronic_ISBN :
0-7803-9736-3
DOI :
10.1109/ICOSP.2006.345996
