Title :
Current estimation in MOS IC logic circuits
Author :
Chowdhury, S. ; Barkatullah, J.S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Abstract :
Estimation of currents in NMOS/CMOS IC logic circuits at the gate and macro levels is considered. The estimates are to be used for reliable design of power and ground buses. An accurate and efficient model of a gate is used to develop algorithms to estimate the maximum currents. The algorithms provide a tradeoff between run time and the quality of solution. Experimental results are included.<>
Keywords :
MOS integrated circuits; circuit CAD; circuit analysis computing; electric current; integrated logic circuits; CMOS IC; MOS IC logic circuits; NMOS IC; algorithms; current estimation; gate level currents; gate model; ground buses; macro level currents; maximum currents; power buses; reliable design; run time; solution quality; CMOS logic circuits; CMOS technology; Cities and towns; Engineering drawings; Integrated circuit technology; Logic circuits; Logic design; MOS devices; Upper bound; Voltage;
Conference_Titel :
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-0869-2
DOI :
10.1109/ICCAD.1988.122496
