Power/performance optimization in FPGA-based asymmetric multi-core systems

In embedded systems, energy efficiency is the new fundamental performance limiter. Considering that, many techniques were applied at different development levels, such as co-design, compilers, schedulers, run-time management, and applications. The fusion of techniques from different levels has also been exploited to increase the optimization opportunities. In this paper, we present a work in progress tool to exploit power/performance optimization techniques in FPGA-based asymmetric multi-core systems. The tool performs optimizations in two phases: compilation and execution. In compilation, are generated from a compiler the hardware and software configurations of a multi-core architecture based on LEON3 processor. During execution, information about application properties, available hardware resources, and system behavior is used to do thread scheduling, clock gating, and dynamic frequency scaling (DFS).