Title :
Thermal-aware partitioning for 3D FPGAs
Author :
Nunna, Krishna Chaitanya ; Mehdipour, Farhad ; Murakami, Kazuaki
Author_Institution :
Dept. of Adv. Inf., Kyushu Univ., Fukuoka, Japan
Abstract :
Three-dimensional FPGA is one of the promising innovations which can lead to the reduction in delay, area and power. There is an absolute necessity to develop algorithms and software tools to exploit the advantages of the third dimension, and to solve complex tasks associated with them. Also, thermal issues are cited as critical concern in 3D integration which results in degradation of device performance. In this paper we are proposing an idea for thermal-aware partitioning targeting the power/thermal-aware EDA flow for 3D FPGAs.
Keywords :
delays; field programmable gate arrays; 3D FPGA; 3D integration; delay reduction; power-thermal-aware EDA flow; software tools; thermal-aware partitioning; three-dimensional FPGA; Density measurement; Estimation; Field programmable gate arrays; Partitioning algorithms; Power system measurements; Routing; Thermal analysis;
Conference_Titel :
Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on
Conference_Location :
Oslo
Print_ISBN :
978-1-4673-2257-7
Electronic_ISBN :
978-1-4673-2255-3
DOI :
10.1109/FPL.2012.6339198
