Datapath library reuse in the design of a high performance floating point unit

Author

Hossain, Razak ; Herbert, Jeffrey C. ; Gouger, Jason E. ; Bechade, Roland

Author_Institution

Mentor Graphics Corp., Warren, NJ, USA

fYear

1998

fDate

13-16 Sep 1998

Firstpage

277

Lastpage

280

Abstract

This paper describes the use of a datapath library in the design of a high performance, pipelined floating point unit (FPU) macrocell. The existence of the intellectual property (IP) library allowed the rapid completion of the FPU within the context of a high performance structured custom design flow. The 165000 transistor floating point unit was completed in 25 man months from initial customer specification to final physical assembly. The macrocell occupies 2.45 mm×2.55 mm in a 0.35 μm, 4 metal CMOS process and has a simulated cycle time of 5.2 ns at 3.3 V and 85°C

Keywords

CMOS logic circuits; application specific integrated circuits; cellular arrays; circuit simulation; floating point arithmetic; industrial property; logic CAD; pipeline arithmetic; software libraries; 0.35 micron; 3.3 V; 5.2 ns; 85 degC; CMOS process; datapath library reuse; intellectual property library; macrocell; pipelined floating point unit; simulated cycle time; structured custom design flow; Adders; CMOS process; Circuits; Clocks; Delay; Detectors; Graphics; Libraries; Logic design; Macrocell networks;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International

Conference_Location

Rochester, NY

ISSN

1063-0988

Print_ISBN

0-7803-4980-6

Type

conf

DOI

10.1109/ASIC.1998.722994

Filename

722994