Design of Floating-point Operation Based on FPGA and it´s Application

This paper introduces the design of floating-point (FP) arithmetic units in common use based on FPGA, including the conversion between FP data and fixing-point data, FP addition, subtraction, multiplication and division. All of them are pipeline architectures and specified in VHDL, are fully synthesizable with performance comparable to other available high speed implementations. Special emphasis is put on the application of FP data in radar. As an example, the FP operation modules are used in quadrature sampling of intermediate frequency (IF) signal, to show that a much higher performance can be obtained.