Title :
Sequential circuit testing: from DFT to SFT
Author :
Chou, Richard M. ; Saluja, Kewal K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Abstract :
Sequential circuit testing is an active research area due to its applicability, its practicality, and its complexity. This paper gives an overview of the sequential automatic test pattern generation approaches and the classical and more recent design-for-testability methods. However, recent trend is to move towards synthesis-for-testability (SFT) approach. In this paper, we describe some of the work done by others as well as our current research using SFT techniques. In particular, the ability to perform SFT on large sequential circuits is discussed
Keywords :
VLSI; automatic testing; design for testability; integrated circuit design; integrated circuit testing; integrated logic circuits; logic design; logic testing; sequential circuits; state assignment; ATPG; DFT techniques; SFT techniques; automatic test pattern generation; design-for-testability methods; large sequential circuits; sequential circuit testing; synthesis-for-testability; Automatic test pattern generation; Circuit faults; Circuit synthesis; Circuit testing; Costs; Design for testability; Logic design; Logic testing; Sequential analysis; Sequential circuits;
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-8186-7755-4
DOI :
10.1109/ICVD.1997.568089
