DocumentCode
1947108
Title
Design, simulation and hardware validation of a low-cost CLMS echo canceling system
Author
Prieto, Pablo ; Sanchez, Mikel ; Del Ser, Javier ; Mendicute, Mikel
Author_Institution
TECNALIA-Telecom, Zamudio, Spain
fYear
2009
fDate
June 28 2009-July 1 2009
Firstpage
1
Lastpage
4
Abstract
This paper presents the design, simulation and performance of a low-cost echo canceler for its application to on-channel repeaters in single frequency DVB-T networks. In these devices an echo canceler is required in order to avoid the coupling echoes produced between transmission and reception antennas. The designed echo canceler is based on an adaptive FIR filter where a correlation-based LMS algorithm (namely, CLMS) is used for updating the set of complex coefficients under a minimum squared error (MSE) criteria. The implemented prototype includes an analog devices floating-point DSP and a Virtex II Pro FPGA core. Computer simulation results and the registered in-lab measurements of the prototype verify that our approach shows surprisingly satisfactory echo attenuation capabilities at a minimal computational cost.
Keywords
adaptive filters; digital video broadcasting; echo suppression; field programmable gate arrays; repeaters; Virtex II Pro FPGA core; adaptive FIR filter; analog devices floating-point DSP; echo attenuation; echo canceling system; minimum squared error criteria; on-channel repeaters; reception antennas; single frequency DVB-T networks; transmission antennas; Algorithm design and analysis; Computer errors; Couplings; Digital video broadcasting; Finite impulse response filter; Frequency; Hardware; Least squares approximation; Repeaters; Transmitting antennas;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems and TAISA Conference, 2009. NEWCAS-TAISA '09. Joint IEEE North-East Workshop on
Conference_Location
Toulouse
Print_ISBN
978-1-4244-4573-8
Electronic_ISBN
978-1-4244-4574-5
Type
conf
DOI
10.1109/NEWCAS.2009.5290486
Filename
5290486
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