Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits

In nano-scaled CMOS circuits, the random dopant fluctuations cause significant threshold voltage (Vt) variations in transistors. In this paper, we propose a semi-analytical estimation methodology to predict the delay distribution (mean and standard deviation) of logic circuits considering Vt variation in transistors. The proposed method is fast and can be used to predict delay distribution in nano-scaled CMOS technologies both at the circuit and the device design phase.