VLSI implementation of sliding window DFT

Sliding DFT analysis is done to calculate the spectrum of the input signal on sample by sample basis. It is very effective technique available to identify the random and abrupt faults in the input data. Spikes constrained in time domain data are spread out in frequency domain corrupting the frequency data and in some cases masking the weak signal in adjacent frequency bins. Using sliding DFT we can isolate the spike from input data or recognize the occurrence and take necessary processing precautions preventing the corrupted data to be passed on for further processing. The sudden discontinuity is identified by sudden increase in side lobe levels of the Doppler filter bank. The effect of the disturbance persists for data length of `2N -1´. But by setting appropriate thresholds it can be identified and can be isolated. In this paper we present hardware architecture to perform the sliding window DFT on FPGA. The architecture is difficult to implement using vendor supplied IP cores as they are designed to work for block input and not by sample by sample data flow. In block data flow it can be identified but cannot be resolved precisely. And since there is no provision to access the twiddle factors in IP cores which form the crux of FFT processing, SDFT realized using IP cores cannot be further optimized thus reducing its configurability. To achieve sliding DFT we have designed customized and configurable DFT block and structured the data flow using memory arrays to realize sliding window operation.