Intra-chip physical parameter sensor for FPGAS using flip-flop metastability

We present a novel intra-chip physical parameter sensor that exploits the clock-to-q delay response of flip-flops. The proposed design relies on deliberately violating the setup and hold time conditions of a flip-flop to bring it into metastable states and increase its clock-to-q delay. Traditionally, this is an undesired effect because it can result in unpredictable system failures. In this work, this phenomenon is exploited to quantify variations in intra-chip physical parameters. Our design has three benefits over conventional ring-oscillator-based sensors; it consumes less device resources, has a higher precision and does not require a high clock frequency. We present a small-signal model of the proposed sensor and compare its performance with ring oscillators by conducting voltage and temperature-controlled experiments on an Altera Cyclone II FPGA device.