DocumentCode
1947178
Title
Optimizing test hardware for at-speed testing of datapaths in an integrated circuit
Author
Bhattacharya, Debashis ; Freeman, Smith ; Lin, Bill
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
1997
fDate
4-7 Jan 1997
Firstpage
289
Lastpage
296
Abstract
In this paper, we introduce a new representation method for datapath tests-called test template representation-and also introduce a new analysis technique to minimize the test logic overhead, through careful processing of the test templates. The resultant test structures represent the next systematic step beyond the multiplexer bypass method commonly found in commercial test tools
Keywords
VLSI; design for testability; integrated circuit design; integrated circuit testing; logic design; logic testing; analysis technique; at-speed testing; datapaths; integrated circuit; representation method; test hardware optimisation; test logic overhead minimisation; test template representation; Automatic testing; Built-in self-test; Circuit testing; Design for testability; Hardware; Integrated circuit testing; Logic testing; Manuals; Multiplexing; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location
Hyderabad
ISSN
1063-9667
Print_ISBN
0-8186-7755-4
Type
conf
DOI
10.1109/ICVD.1997.568092
Filename
568092
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