Title :
New BIST techniques for universal and robust testing of CMOS stuck-open faults
Author :
Das, Debesh K. ; Chakraborty, Susanta ; Bhattacharya, Bhargab B.
Author_Institution :
Dept. of Comput. Sci. & Eng., Jadavpur Univ., Calcutta, India
Abstract :
This paper presents three built-in self-test (BIST) schemes for robust testing of stuck-open faults in combinational FCMOS complex cells of arbitrary structure. The first method shows that all single stuck-open faults can be robustly tested by applying a universal sequence of 5×2n vectors to the modified circuit under test (CUT), and counting the number of 1´s in the output response. The second method uses the same test pattern generator (TPG), but faults are detected by a self comparison technique without the need of storing a signature. Finally, we propose a new adaptive BIST technique, where the TPG is driven by the past outputs of the CUT itself In all the cases, the TPG is universal, i.e., if does not depend on the functionality and the structure of the CUT, but does ensure robust testing. Neither any test vector, nor any fault dictionary, is required. These approaches provide simplicity, less testing time and test data, and compare favorably with earlier BIST designs for CMOS circuits
Keywords :
CMOS logic circuits; built-in self test; combinational circuits; fault diagnosis; integrated circuit testing; logic testing; BIST techniques; CMOS stuck-open faults; adaptive BIST technique; built-in self-test schemes; combinational FCMOS complex cells; self comparison technique; simplicity; test pattern generator; testing time; universal robust testing; universal vector sequence; Built-in self-test; Circuit faults; Circuit testing; Delay; Electrical fault detection; Electronic equipment testing; Fault detection; Hamming distance; Robustness; Test pattern generators;
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-8186-7755-4
DOI :
10.1109/ICVD.1997.568094