Title :
Accuracy of channel resistance and current gain methods of Leff extraction
Author :
Bhattacharya, S.S. ; Worley, A.R. ; Williams, R.A.
Author_Institution :
Digital Commun. Div., Rockwell Int. Corp., Newport Beach, CA, USA
Abstract :
In this paper, we report a physically based interpretation of the MOSFET effective channel length, Leff. Leff of a MOSFET is usually extracted from measurements of the linear region current gain (1/K method) or the linear region resistance (resistance method) on transistors with different gate lengths. We find that the extracted Leff of a submicron lightly doped drain/source (LDD) MOSFET is strongly influenced by diffusion of minority carriers (electrons for NMOSFETs) from the gate-controlled LDD overlap region into the inversion layer. This changes the resistance of the inversion layer at the source/drain ends and thus causes the extracted Leff to deviate from the metallurgical channel length, Lmet. The impact of minority carrier diffusion is stronger for shorter channel lengths; therefore, the extracted ΔL(=Lgate-Leff where Lgate is the drawn gate length) increases with decreasing gate length. The choice of gate lengths used in Leff extraction will, thus, influence the value for Leff. MINIMOS 2D simulations have been used to study this effect. The results have been confirmed by actual measurements on submicron LDD MOSFETs. This analysis has been used to select the best choices of Lgate and bias condition to minimize errors in the measurement of Leff
Keywords :
carrier lifetime; insulated gate field effect transistors; minority carriers; semiconductor device models; bias condition; channel resistance; current gain method; effective channel length; gate-controlled LDD overlap region; inversion layer; lightly doped drain; minority carrier diffusion; parameter extraction; submicron LDD MOSFETs; CMOS technology; Current measurement; Digital communication; Electric resistance; Electrical resistance measurement; Electrons; Gain measurement; Length measurement; Lighting control; MOSFET circuits;
Conference_Titel :
Microelectronic Test Structures, 1994. ICMTS 1994. Proceedings of the 1994 International Conference on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-1757-2
DOI :
10.1109/ICMTS.1994.303477