DocumentCode
1947238
Title
A 10Gb/s data-dependent jitter equalizer
Author
Buckwalter, James ; Hajimiri, Ali
Author_Institution
California Inst. of Technol., Pasadena, CA, USA
fYear
2004
fDate
3-6 Oct. 2004
Firstpage
39
Lastpage
42
Abstract
An equalization circuit is presented that reduces data-dependent jitter by aligning data transition deviations. This paper presents an analytic solution to data-dependent jitter and demonstrates its impact on the phase noise of the recovered clock. A data-dependent jitter equalizer is presented that compensates for impairment of the channel and lowers the phase noise of the recovered clock. The circuit is implemented in a SiGe BiCMOS process and operates at 10 Gb/s. It suppresses phase noise resulting from data-dependent jitter by 10 dB.
Keywords
BiCMOS integrated circuits; equalisers; phase noise; synchronisation; timing jitter; 10 Gbit/s; BiCMOS; SiGe; data transition deviation alignment; data-dependent jitter equalizer; equalization circuit; phase noise suppression; recovered clock phase noise; timing jitter; Bandwidth; Bit error rate; Circuits; Clocks; Data analysis; Equalizers; Optical transmitters; Phase noise; Silicon germanium; Timing jitter;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004
Print_ISBN
0-7803-8495-4
Type
conf
DOI
10.1109/CICC.2004.1358728
Filename
1358728
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