A small-area parallel-pipeline architecture for MTO-convolutional encoders

In this paper, we propose a new parallel-pipeline approach to design small-area low complexity convolutional encoders, suitable for high data throughput communication applications. This approach can apply both to the OTM (one to many) and the MTO (many to one) encoder schemes. Here, we will discuss the problem of designing a low cost parallel-pipeline encoder for the MTO case. The new architecture has been implemented on FPGA devices of the Altera Stratix II family, for complexity and performance evaluation on several convolutional codes. The experimental results clearly show that the new architecture outperforms the former ones, including those we proposed in for OTM and MTO. Indeed, similar bit rates have been achieved with noticeable area consumption reduction (up to 6.96 Gbits/s achieved with a 50% smaller circuit in the case of 32-bit parallel implementations).