• DocumentCode
    1947346
  • Title

    Sliding block Viterbi decoders in FPGA

  • Author

    Véstias, Mário ; Neto, Horácio ; Sarmento, Helena

  • fYear
    2012
  • fDate
    29-31 Aug. 2012
  • Firstpage
    595
  • Lastpage
    598
  • Abstract
    In this paper, we analyze the design of sliding block Viterbi decoders in FPGA based on two proposed parallel Viterbi decoders with different area/performance ratios. Viterbi decoders for two wireless technologies were designed considering the proposed Viterbi decoders achieving reductions in resource utilizations of more than 50% compared to other state-of-the-art proposals1.
  • Keywords
    Viterbi decoding; block codes; field programmable gate arrays; radio networks; FPGA; parallel Viterbi decoders; sliding block Viterbi decoders; wireless technology; Decoding; Field programmable gate arrays; Synchronization; Table lookup; Viterbi algorithm; Wireless communication;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on
  • Conference_Location
    Oslo
  • Print_ISBN
    978-1-4673-2257-7
  • Electronic_ISBN
    978-1-4673-2255-3
  • Type

    conf

  • DOI
    10.1109/FPL.2012.6339215
  • Filename
    6339215
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1947346