A visual approach for asynchronous circuit synthesis

Author

Nagalla, Radhakrishna ; Hellestrand, Graham

Author_Institution

Dept. of Comput. & Syst. Technol., New South Wales Univ., Kensington, NSW, Australia

fYear

1997

fDate

4-7 Jan 1997

Firstpage

329

Lastpage

335

Abstract

A new approach for the synthesis of asynchronous interface circuits from the Signal Transition Graph (STG) specifications is discussed. As a novel contribution we propose a visual path-oriented algorithm to ascertain whether a given STG has Complete State Coding (CSC) property. Unlike most of the existing algorithms which operate on a state graph, this algorithm operates on the STG. This approach has the advantage of being either easily automated or easier to visually correlate with the STG specifications and to perform by a paper and pencil. Experimental results with a large number of practical asynchronous bench marks are presented

Keywords

Petri nets; asynchronous circuits; logic CAD; minimisation of switching nets; visual programming; C language implementation; asynchronous bench marks; asynchronous circuit synthesis; asynchronous interface circuits; complete state coding; easy automation; free-choice Petri net; signal transition graph specifications; state minimisation; visual approach; visual path-oriented algorithm; Asynchronous circuits; Circuit synthesis; Computer interfaces; Computer science; Concurrent computing; Data structures; Logic circuits; Moon; Petri nets; Signal synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1997. Proceedings., Tenth International Conference on

Conference_Location

Hyderabad

ISSN

1063-9667

Print_ISBN

0-8186-7755-4

Type

conf

DOI

10.1109/ICVD.1997.568099

Filename

568099