Visualising reconfigurable libraries for FPGAs

This paper describes a framework and tools for visualising hardware libraries for field-programmable gate arrays (FPGAs), which should also be useful for circuit design in general. Our approach integrates the visualisation of design behaviour and structure, supports various simulation modes, and assists the development of run-time reconfigurable designs in FPGAs such as Xilinx 6200 devices. Our tools can automatically generate a block diagram from a concise parametrised description. Design operations are animated by projecting a dataflow model on the block diagram. The user can select to view data valves on specific input and output ports and internal paths. Numerical, symbolic and bit-level simulation and their combination are supported, and the animation speed can be adjusted. The tools should benefit both library users and suppliers, since they can be used (a) to show the internal structure of a design, (b) to illustrate effective usage of library components, and (c) to present the consequences of parametrising designs in different ways.