• DocumentCode
    1947391
  • Title

    Dual-core motion estimation processor

  • Author

    Olivares, Joaquín ; Palomares, Jose M.

  • Author_Institution
    Dept. of Comput. Archit., Electron. & Electron. Technol., Univ. of Cordoba, Córdoba, Spain
  • fYear
    2012
  • fDate
    29-31 Aug. 2012
  • Firstpage
    603
  • Lastpage
    606
  • Abstract
    This paper presents a motion estimation processor based on a dual-core architecture. Both cores are based on bit-serial adder trees. Memory structures are also described. This architecture is bit-precision reconfigurable. Performance results for several smartphones and tablets are presented. Furthermore, hardware results and comparison with other works are included. Real-time processing is achieved for all devices studied.
  • Keywords
    adders; microprocessor chips; motion estimation; reconfigurable architectures; bit-precision reconfigurable architecture; bit-serial adder trees; dual-core architecture; dual-core motion estimation processor; memory structures; smart phone; tablets; Abstracts; Logic gates; Table lookup;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on
  • Conference_Location
    Oslo
  • Print_ISBN
    978-1-4673-2257-7
  • Electronic_ISBN
    978-1-4673-2255-3
  • Type

    conf

  • DOI
    10.1109/FPL.2012.6339217
  • Filename
    6339217
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1947391