Automated gated diode measurements for device characterization

The MOS semiconductor manufacturing process includes many processing steps to modify the electrical characteristics of the gate/drain region of the MOS transistor. The gated diode test structure has been known to be an excellent tool for characterizing this region. However, this measurement has been difficult to make due to the highly accurate and repeatable sub-picoampere measurements required for this test structure. Therefore, this measurement has only been made in small quantities with elaborate test circuit methods on custom bench top wafer level electrical test systems, reducing the effectiveness of the electrical test results. SEMATECH has implemented this measurement on an automated production electrical test system used for both in-line and end-of-line process control data collection. The measurement method produces results such as flat band voltage (Vfb), threshold voltage (Vt), fast surface state leakage (Ifss), and reverse diode leakage (Ird). Analysis of the measurement produces bulk and junction perimeter defect identification as well as qualitative measures of changes in Vfb, Vt, and surface states. Automating this measurement allows statistically significant samples to be collected, accelerating analysis of the gate/drain region and providing spatial characterization across the wafer. SEMATECH is using this measurement method to characterize the damage that results from using plasma etch, deposition, and implant processes. Many SEMATECH member companies have already adopted these methods by taking advantage of the SEMATECH technology transfer process to receive design tapes of the test structures and test tapes of the measurement method. The measurement method was written for HP´s ICMS test executive software that controls the HP4062UX test system for semiconductor process characterization and production process control