The effect of etch residuals on via reliability

Vias are formed in interconnect structures using a polymerizing chemistry in order to avoid etching the underlying metal wires. However, a drawback of the polymerizing chemistry is that etch residues can remain in the via opening, resulting in high via resistance and possible degradation of circuit performance. Although it is well known that etch residues in vias can cause yield loss, the effect on reliability has not been reported for submicron vias. In this paper, the effect of etch residues on via reliability is studied. Vias with etch residues showed no degradation in reliability after a thermal cycle stress, high temperature storage, or humidity stress. However, vias with etch residues fail at a lower current during a wafer level voltage ramp electromigration stress, compared to residue-free vias, suggesting that etch residues will reduce the electromigration lifetime of interconnect structures.