Title :
Asynchronous implementation of synchronous Esterel specifications
Author :
Mitra, Raj S. ; Bhattacharya, Bishnupriya ; Lavagno, Luciano
Author_Institution :
Cadence Design Syst. Pvt. Ltd., Uttar Pradesh, India
Abstract :
The synchrony hypothesis of Esterel demands the generation of a single monolithic FSM from the specifications. However for large specifications, the size of this FSM can prove to be inhibitively large. In this paper, we propose a practical solution to this problem, which generates separate FSMs for each of the concurrent instructions. We also enumerate the deviations in semantics due to this translation algorithm so that the user is aware of the executable semantics that he should expect
Keywords :
asynchronous circuits; finite state machines; logic CAD; software engineering; specification languages; FSM generation; asynchronous implementation; concurrent instructions; executable semantics; hardware-software codesign; large specifications; separate FSMs; synchronous Esterel specifications; translation algorithm; Broadcasting; Circuit synthesis; Delay; Embedded software; Embedded system; Hardware; Integrated circuit interconnections; Merging; Software systems; Very large scale integration;
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-8186-7755-4
DOI :
10.1109/ICVD.1997.568106
