DocumentCode :
1947479
Title :
Implementation of (255,223) Reed Solomon minimal instruction set computing using Handel-C
Author :
Ong, Jia Jan ; Ang, L.-M. ; Seng, K.P.
Author_Institution :
Dept. of Electr. & Electron., Univ. of Nottingham Malaysia, Semenyih, Malaysia
Volume :
9
fYear :
2010
fDate :
9-11 July 2010
Firstpage :
49
Lastpage :
54
Abstract :
Reed Solomon coding plays an important role in sustaining the integrity of the data transmitted across communication channel. The Reed Solomon encoder can be embedded into many devices to protect the data to become corrupted. However, the encoder does consume a significant amount of power. By integrating the encoder circuit, there would be an increase of hardware component to be embedded in the device. Both of these factors give raise to the cost of producing the device. With the continuation of previous work, implementation of (15,9) Reed Solomon minimal instruction set computing on FPGA using Handel-C, a (255,223) Reed Solomon encoder was develop on the MISC processor. This encoder has a simple circuit which will produce the same encoded codeword as produced by usual encoder.
Keywords :
Reed-Solomon codes; computer architecture; data integrity; embedded systems; error correction codes; field programmable gate arrays; telecommunication channels; (255,223) Reed Solomon minimal instruction set computing; FPGA; MISC processor; Reed Solomon coding; communication channel; data integrity; encoder circuit; handel-C; Clocks; Computer languages; Table lookup; Minimal Instruction Set Computing; One Instruction Set Computing; Reed Solomon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Science and Information Technology (ICCSIT), 2010 3rd IEEE International Conference on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4244-5537-9
Type :
conf
DOI :
10.1109/ICCSIT.2010.5564488
Filename :
5564488
Link To Document :
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