DocumentCode
1947521
Title
Worst-case MOSFET parameter extraction for a 2 μm CMOS process
Author
Burke, K. ; Power, J.A. ; Donnellan, B. ; Moloney, K. ; Lane, W.A.
Author_Institution
Analog Devices B.V., Limerick
fYear
1994
fDate
22-25 Mar 1994
Firstpage
119
Lastpage
125
Abstract
This paper will describe the process by which realistic nominal and worst-case DC MOSFET model parameter sets were determined and validated for a 2 μm CMOS technology. The steps involved in this task, which will be detailed, ranged from the definition of a suitable circuit simulator model, through the collection of statistical parametric data, to the generation and verification of the worst-case model sets obtained from this data
Keywords
CMOS integrated circuits; circuit analysis computing; insulated gate field effect transistors; semiconductor process modelling; statistical analysis; 2 micron; CMOS technology; circuit simulator model; model parameter sets; parameter extraction; statistical parametric data; worst-case DC MOSFET model; CMOS process; CMOS technology; Circuit simulation; Circuit synthesis; Equations; MOSFET circuits; Parameter extraction; Predictive models; Semiconductor device modeling; Surface resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 1994. ICMTS 1994. Proceedings of the 1994 International Conference on
Conference_Location
San Diego, CA
Print_ISBN
0-7803-1757-2
Type
conf
DOI
10.1109/ICMTS.1994.303491
Filename
303491
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