A 65nm CMOS EDGE/UMTS/WLAN tri-mode four-channel time-interleaved ΣΔ ADC

A four-channel time-interleaved SigmaDelta analog-to-digital-converter for EDGE/UMTS/WLAN tri-mode zero-IF receiver is presented. The number of time-interleaved channels, the clock rate and the order of the modulators are programmable. The former adapts the conversion bandwidth to the selected standard while the two last are set to reach dynamic range specifications. Each channel uses a Global Multi-Stage Closed-Loop SigmaDelta modulator which is a novel cascade 2-2 topology. A Sample-And-Hold circuit is used at the front-end of the ADC to reduce the clock skew issue inherent to time-interleaved converters. The prototype chip was implemented in a 1.2 V 65 nm CMOS process using metal-insulator-metal capacitors. Simulated dynamic range is 80 dB/80 dB/50 dB in 135 KHz/2 MHz/12.5 MHz respectively. The number of active channels in EDGE/UMTS/WLAN mode is one, two and four respectively which leads to a power consumption of 3.1 mW/55.2 mW/110.4 mW. Clocked at 208 MHz, the analog front-end exhibits an SFDR less than -90 dB over 2 MHz bandwidth and consumes 12 mW. The total active die area is 2.2 mm².