An efficient hardware architecture of the optimised SIFT descriptor generation

Scale Invariant Feature Transform (SIFT) algorithm has the potential of detecting a large number of features from images, which makes the feature descriptor generation become a bottleneck of the processing speed and hence degrade the overall performance of the algorithm. To tackle this problem, we propose an efficient hardware architecture based on the polar sampled descriptor in this paper. It takes only 7.57us to generate a feature descriptor of 72 dimensions with a system frequency of 100MHz, which is equivalent to approximately 132100 feature descriptors per second. It can generate feature descriptors for VGA (640×480 pixels) resolution video at 60 frames per second (fps), provided that there are no more than 2200 features per frame. As far as we know, our hardware architecture has the highest processing speed for descriptor generation, compared with other existing architectures.